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sci-electronics
/
iverilog
A Verilog simulation and synthesis tool
http://iverilog.icarus.com
Overview
Dependencies
QA report
Pull requests
0
Bugs
6
Security
0
Changelog
Bug Reports
sci-electronics/iverilog-12.0 - invalid option: --verbose
904480 - Assigned to vowstar
sci-electronics/iverilog-11.0 - mv: cannot move cprop.d to dep/cprop.d: No such file or directory
880921 - Assigned to vowstar
sci-electronics/iverilog-12.0 - "./lexor.lex", line 4: unrecognized %option: reentrant
908459 - Assigned to vowstar
sci-electronics/iverilog-12.0 - make: [Makefile:<snip>: all] Error 2
911647 - Assigned to vowstar
sci-electronics/iverilog-12.0 - [ncurses-6.5] [meson] [libtool] [gcc-15] parse.cc: error: type yysymbol_kind_t violates the C++ One Definition Rule [-Werror=odr]
940595 - Assigned to vowstar
sci-electronics/iverilog-12.0 - mv: cannot move PNamedItem.d to dep/PNamedItem.d: No such file or directory
917344 - Assigned to vowstar
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Packages Bugs (6)
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